Partial Pseudo-Random Hashing for Transactional Memory Read/Write Data Processing and Validation

Authors

G M Sridevi, Research Scholar, JSS Academy of Technical Education (Affiliated to Visvesvaraya Technological University, Belagavi)Follow
Ashoka D V, Department of Information Science and Engineering, JSS Academy of Technical Education, Bengaluru, IndiaFollow
B V Ajay Prakash, VTU-RC, Belagavi, IndiaFollow

Abstract

Development of a bypass parallel processing block is one of the emerging and interesting research areas in memory read/write application domain. Many Random Number Generation (RNG) techniques have been introduced for processing the data in storage memory. But the limitations include reduced efficiency, increased computational complexity, high area consumption and higher cost. This paper presents a novel dynamic memory register with optimal XOR design based on partial pseudo-random hashing to process transactional memory read/write data. Transfer characteristics of the current are analysed based on the pseudo differential pair for proficient memory utilization. A memory window is then created and adjusted for obtaining an optimal power flow with lesser data loss. The performance of the proposed design is evaluated using different performance measures. The power consumed for processing the data using the proposed design is reduced to nearly 25% when compared to other proposed designs along with reduced component usage. Delay is reduced to 2.31ns and a 15% improvement in frequency and nearly 4% increase in throughput is seen when compared to existing methods.

Recommended Citation

Sridevi, G M; D V, Ashoka; and Prakash, B V Ajay (2022) "Partial Pseudo-Random Hashing for Transactional Memory Read/Write Data Processing and Validation," Karbala International Journal of Modern Science: Vol. 8 : Iss. 2 , Article 7.
Available at: https://doi.org/10.33640/2405-609X.3223

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